A MODEL FOR INTERDIFFUSION AT METAL SEMICONDUCTOR INTERFACES: CONDITIONS FOR SPIKING (2025)

Metal-Semiconductor Interfaces with Novel Structural and Electrical Properties: Metal Cluster Deposition

MRS Proceedings, 1989

Physics of Semiconductor Devices

Springer eBooks, 2018

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The Journal of Microelectronic Research

2006

These proceedings contain papers presented at the 24th Annual Microelectronic Engineering Conference held at the Rochester Institute of Technology (RIT) on May 16 through 17, 2006 by senior undergraduate students of Microelectronic Engineering of RIT. The students graduating with BS degree in Microelectronic Engineering are required to take a two-course sequence of capstone design courses, 0305-681 and 0305-691 entitled Senior Design Project I and II in their fifth year. The first course consists of submission of a research proposal, related to the field of semiconductor devices and processing, by each student. Following the approval of the proposal, the students carry out their projects through the ten-week spring quarter. Toward the end of the spring quarter, the students are required to present their work at the Microelectronic Engineering Conference held at RIT annually in the month of May and publish in this Journal of Microelectronic Research.

Semiconductor Microelectronics and Nanoelectronics Programs

2009

The NSMP has stimulated a greater interest in semiconductor metrology, motivating most of NIST's laboratories to launch additional projects of their own and to cost-share OMP-funded projects. The projects described in this book represent this broader portfolio of microelectronics projects. Most, but not all, of the projects described are partially funded by the NSMP, which is providing a $12 million budget in fiscal year 2008. FoStering niSt'S relationSHiPS WitH tHe induStry By the late 1980s, NBS (now NIST) recognized that the semiconductor industry was applying a much wider range of science and engineering technology than the existing NIST program was designed to cover. The necessary expertise existed at NIST, but in other parts of the organization. In 1991, NIST established the Office of Microelectronics Programs (OMP) to coordinate and fund metrological research and development across the agency, and to provide the industry with easy single point access to NIST's widespread projects. Roadmaps developed by the U.S. Semiconductor Industry Association v Semiconductor Microelectronics and Nanoelectronics Programs v Welcome and introduction (SIA) have independently identified the broad technological coverage and growing industrial needs for NIST's semiconductor metrology developments. As the available funding and the scope of the activities grew, the collective name became the National Semiconductor Metrology Program (NSMP), operated by the OMP. The NSMP has stimulated a greater interest in semiconductor metrology, motivating most of NIST's laboratories to launch additional projects of their own and to cost-share OMP-funded projects. The projects described in this book represent this broader portfolio of microelectronics projects. Most, but not all, of the projects described are partially funded by the NSMP, which is providing a $12 million budget in fiscal year 2009. Additionally, in 2007, the US Congress added approximately $3M to OMP's budget to be used in support of external work on beyond CMOS. Beyond CMOS is a term that describes the search for a new switch to replace the presently available CMOS switch which is reaching the limit of its useful life. This money has been granted to the Nanotechnology Research Initiative (NRI) which is a subsidiary of the Semiconductor Research Corporation (SRC). FoStering niSt'S relationSHiPS WitH tHe induStry NIST's relationships with the SIA, SEMATECH and its subsidiary, International SEMATECH Manufacturing Initiative (ISMI), and the Semiconductor Research Corporation (SRC) are also coordinated through the OMP. Staff from OMP and NIST Laboratories represents NIST on the SIA committees that develop the International Technology Roadmap for Semiconductors (ITRS), as well as on numerous SRC Technical Advisory Boards. NIST staff is also active in the International National Electronics Manufacturers Initiative (iNEMI), the EIA, the International Organization for Standardization (ISO), and Semiconductor Equipment and Materials International (SEMI). NIST supports the United States National Committee Technical Advisory Group for the International Electrotechnical Commission Technical Committee TC113 on Nanotechnology Standardization for Electrical and Electronic Products and Systems (Technical Advisor, USNC TAG for IEC TC 113 on nanotechnology) by funding the Technical Advisor to that organization. learn more about Semiconductor metrology at niSt This publication provides summaries of NIST's metrology projects for the silicon semiconductor industry and their suppliers of materials and manufacturing equipment. Each project responds to one or more metrology requirements identified by the industry in sources such as the ITRS. NIST is committed to listening to the needs of industry, working with industry representatives to establish priorities, and responding where resources permit with effective measurement technology and services.

THEORY OF MODERN ELECTRONIC SEMICONDUCTOR DEVICES

Journal of Microelectronic Research

2014

Copper diffusion into the silicon bulk is a detrimental obstacle to advanced-CMOS and photovoltaic processes that seek to incorporate copper into the metallization steps because of its deep-level trap nature to carriers. Recent studies have hinted that an organic porphyrin or silane-based self-assembled monolayer (SAM) could be a method of prevention to copper diffusion. Inorganic alternatives using TiO2 or Ni may also present a solution. The self-assembly of 5,10,15,20Tetrakis(4-hydroxyphenyl)-21H,23H-porphine (OHTPP) over SiO2 has been examined using atomic-force microscopy (AFM), contact angle measurements, and variable angle spectroscopic ellipsometry (VASE). Results indicate that this particular OHTPP chemistry fails to adsorb to the Si02 substrate. MetalOxide-Semiconductor (MOS) capacitors with varying dielectric stacks with and without Ti02 over Si02 or Si3N4 and gate metals varying between Cu and Ni have been fabricated and analyzed via bias-temperature stress (BTS) capacita...

The Journal of Microelectronic Research 2008

2008

The objective of this project was to investigate the possibility of producing array of microplasma, having aluminum and silicon electrodes, and oxide as a dielectric with cavity size as large as 30x30 pm2. One of the potential applications among many was to use such device as a photodector. A new class of photodectors, hybrid semiconductor-microplasma devices, to exhibit photoresponsivities in the visible and near infrared that are more than an order of magnitude larger than those typical of semiconductor avalanche photodiodes [1]. After fabrication processing, the route causes of failure were determined. Processing problems were diagnosed and process evaluation test structures characterized using optical microscope, and scanning electron microscopy (SEM). Oxide insulation between the metal layers (Aluminum) was tested using a multimeter. Continuity tests revealed a short between the metal electrodes. The application of SEM in this failure analysis of a finished device shows aluminu...

ACOUSTOELECTRIC INVESTIGATION OF DEEP CENTERS IN BULK AND MULTILAYERED SEMICONDUCTORS ACOUSTOELECTRIC INVESTIGATION OF DEEP CENTERS IN BULK AND MULTILAYERED SEMICONDUCTORS

Theoretical tools for semiconductors devices

1996

I n f orma t ion (OSTI) Los Alamos National Laboratory, an affirmative actionlequal opportunity employer, is operated by the University of California for the U.S. Department Of Energy under contract W-7405-ENG-36. By acceptance of this article, the publisher recugnizes that the U.S. Government retains a nonexclusive, royaltyfree license to publish or reproduce the published form of this contribution, or to allow others to do so, for U.S. Government purposes. The Los Alamos National Laboratory requests that the publisher identify this article as work performed under the auspices of the U.S. Department of Energy. Form No. 836 R5 ST2629 1091 DISCLAIMER This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or proctss disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, m mmendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. f .

Future Trends in Microelectronics: Frontiers and Innovations

2013